diff -u gcc-2.95.2/gcc/config/mips/alteon.h.tigon gcc-2.95.2/gcc/config/mips/alteon.h --- gcc-2.95.2/gcc/config/mips/alteon.h.tigon Thu Apr 20 01:40:40 2000 +++ gcc-2.95.2/gcc/config/mips/alteon.h Thu Apr 20 02:23:54 2000 @@ -0,0 +1,56 @@ +/* Definitions of target machine for GNU compiler. Alteon Tigon MIPS. + Copyright (C) 2000 Jamie Lokier. + +This file is not yet part of GNU CC. + +This file is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This file is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Alteon Tigon default target flags: + * - Use soft float (because the hard float mips16.S file doesn't + * assemble with Alteon's modified assembler), + * - Don't use hardware multiply or divide instructions -- don't have them. + * - Turn on a MIPS optimisation that only the GNU linker & assembler + * can handle. + * - -mno-abicalls is already the default. + * - -fno-pic is already the default. + * - Make -mips2 the default. + * - Make -mcpu=r6000 the default. + * - Make -G 0 the default (the GNU assembler/linker handles GP-relative + * addressing without this set to non-zero). + */ + +#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_SOFT_MUL | MASK_SOFT_DIV \ + | MASK_GAS) +#define MIPS_ISA_DEFAULT 2 /* -mips2 */ +#define MIPS_CPU_STRING_DEFAULT "6000" /* -mcpu=r6000 */ +#define MIPS_DEFAULT_GVALUE 0 + +/* Alteon Tigon preprocessor definitions. */ +#define CPP_PREDEFINES "-Dmips -D_mips -D__mips__ \ +-DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__ \ +-DOEM_ALTEON -D__ALTEON__ \ +-Asystem(alteon) -Acpu(mips) -Amachine(mips) -Amachine(tigon)" + +#define SUBTARGET_CPP_SPEC "\ +%{!mhard-float:%{!msingle-float:-D__mips_soft_float}} \ +%{!mhard-mul:-D__mips_soft_mul} \ +%{!mhard-div:-D__mips_soft_div} " + +#define SUBTARGET_ASM_SPEC "\ +%{mAPIC:-APIC} \ +%{!G*:-G 0} \ +%{!mmips-as:%{!mcpu=*:-mcpu=6000}} \ +%{!mips*:-mips2} " diff -u gcc-2.95.2/gcc/config/mips/elf.h.tigon gcc-2.95.2/gcc/config/mips/elf.h --- gcc-2.95.2/gcc/config/mips/elf.h.tigon Thu Mar 23 02:10:32 2000 +++ gcc-2.95.2/gcc/config/mips/elf.h Thu Apr 20 01:40:27 2000 @@ -22,6 +22,8 @@ /* Use ELF. */ #define OBJECT_FORMAT_ELF +#include "mips/alteon.h" + /* Until we figure out what MIPS ELF targets normally use, just do stabs in ELF. */ #ifndef PREFERRED_DEBUGGING_TYPE diff -u gcc-2.95.2/gcc/config/mips/mips.h.tigon gcc-2.95.2/gcc/config/mips/mips.h --- gcc-2.95.2/gcc/config/mips/mips.h.tigon Fri Mar 24 15:31:44 2000 +++ gcc-2.95.2/gcc/config/mips/mips.h Thu Apr 20 01:25:56 2000 @@ -4,6 +4,7 @@ Changed by Michael Meissner (meissner@osf.org). 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and Brendan Eich (brendan@microunity.com). + -msoft-mul/div added by Jamie Lokier This file is part of GNU CC. @@ -325,9 +326,11 @@ #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */ #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */ #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */ -#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */ -#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */ -#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */ +#define MASK_SOFT_MUL 0x00040000 /* Don't generate integer multiplies */ +#define MASK_SOFT_DIV 0x00080000 /* Don't generate integer divides */ +#define MASK_MAD 0x00100000 /* Generate mad/madu as on 4650. */ +#define MASK_4300_MUL_FIX 0x00200000 /* Work-around early Vr4300 CPU bug */ +#define MASK_MIPS3900 0x00400000 /* like -mips1 only 3900 */ #define MASK_MIPS16 0x01000000 /* Generate mips16 code */ #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */ #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */ @@ -416,6 +419,12 @@ #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT) #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT) + /* generate integer mul or div */ +#define TARGET_SOFT_MUL (target_flags & MASK_SOFT_MUL) +#define TARGET_HARD_MUL (! TARGET_SOFT_MUL) +#define TARGET_SOFT_DIV (target_flags & MASK_SOFT_DIV) +#define TARGET_HARD_DIV (! TARGET_SOFT_DIV) + #define TARGET_MAD (target_flags & MASK_MAD) #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX) @@ -514,6 +523,8 @@ "Use ROM instead of RAM"}, \ {"no-embedded-data", -MASK_EMBEDDED_DATA, \ "Don't use ROM instead of RAM"}, \ + {"APIC", 0, \ + "Use Alteon Networks style PIC"}, \ {"eb", MASK_BIG_ENDIAN, \ "Use big-endian byte order"}, \ {"el", -MASK_BIG_ENDIAN, \ @@ -522,6 +533,14 @@ "Use single (32-bit) FP only"}, \ {"double-float", -MASK_SINGLE_FLOAT, \ "Don't use single (32-bit) FP only"}, \ + {"soft-mul", MASK_SOFT_MUL, \ + "Use software integer multiply"}, \ + {"hard-mul", -MASK_SOFT_MUL, \ + "Use hardware integer multiply"}, \ + {"soft-div", MASK_SOFT_DIV, \ + "Use software integer divide"}, \ + {"hard-div", -MASK_SOFT_DIV, \ + "Use hardware integer divide"}, \ {"mad", MASK_MAD, \ "Use multiply accumulate"}, \ {"no-mad", -MASK_MAD, \ @@ -646,7 +665,8 @@ /* Generate three-operand multiply instructions for both SImode and DImode. */ #define GENERATE_MULT3 (TARGET_MIPS3900 \ - && !TARGET_MIPS16) + && !TARGET_MIPS16 \ + && TARGET_HARD_MUL) /* Macros to decide whether certain features are available or not, depending on the instruction set architecture level. */ @@ -1059,7 +1079,7 @@ #define MIPS_VERSION "[AL 1.1, MM 40]" #ifndef MACHINE_TYPE -#define MACHINE_TYPE "BSD Mips" +#define MACHINE_TYPE "Alteon MIPS (Tigon)" #endif #ifndef TARGET_VERSION_INTERNAL @@ -3573,7 +3593,9 @@ return COSTS_N_INSNS (8); \ } \ \ - if (mips_cpu == PROCESSOR_R3000) \ + if (TARGET_SOFT_MUL) \ + return COSTS_N_INSNS (100); /* Arbitrary large value. */ \ + else if (mips_cpu == PROCESSOR_R3000) \ return COSTS_N_INSNS (12); \ else if (mips_cpu == PROCESSOR_R3900) \ return COSTS_N_INSNS (2); \ @@ -3615,8 +3637,10 @@ \ case UDIV: \ case UMOD: \ - if (mips_cpu == PROCESSOR_R3000 \ - || mips_cpu == PROCESSOR_R3900) \ + if (TARGET_SOFT_DIV) \ + return COSTS_N_INSNS (200); /* Arbitrary large value. */ \ + else if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900) \ return COSTS_N_INSNS (35); \ else if (mips_cpu == PROCESSOR_R6000) \ return COSTS_N_INSNS (38); \ diff -u gcc-2.95.2/gcc/config/mips/mips.md.tigon gcc-2.95.2/gcc/config/mips/mips.md --- gcc-2.95.2/gcc/config/mips/mips.md.tigon Tue Jun 29 03:59:20 1999 +++ gcc-2.95.2/gcc/config/mips/mips.md Tue Apr 11 17:47:02 2000 @@ -1642,7 +1642,7 @@ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "" + "TARGET_HARD_MUL" " { if (HAVE_mulsi3_mult3) @@ -1681,7 +1681,7 @@ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16" + "(mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16) && TARGET_HARD_MUL" "mult\\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI") @@ -1694,7 +1694,7 @@ (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=l")) (clobber (match_scratch:SI 5 "=a"))] - "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16" + "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16 && TARGET_HARD_MUL" "* { rtx xoperands[10]; @@ -1731,8 +1731,7 @@ (clobber (match_scratch:SI 5 "=X,3,l")) (clobber (match_scratch:SI 6 "=a,a,a")) (clobber (match_scratch:SI 7 "=X,X,d"))] - "TARGET_MIPS3900 - && !TARGET_MIPS16" + "TARGET_MIPS3900 && !TARGET_MIPS16 && TARGET_HARD_MUL" "* { static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" }; @@ -1787,8 +1786,7 @@ (match_operand:DI 2 "register_operand" "d"))) (clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT" - + "TARGET_64BIT && TARGET_HARD_MUL" " { if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16) @@ -1809,7 +1807,9 @@ (match_operand:DI 2 "register_operand" "d"))) (clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16" + "TARGET_64BIT + && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16 + && TARGET_HARD_MUL" "dmult\\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI") @@ -1822,7 +1822,9 @@ (clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 4 "=l")) (clobber (match_scratch:DI 5 "=a"))] - "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)" + "TARGET_64BIT + && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16) + && TARGET_HARD_MUL" "* { if (GENERATE_MULT3) @@ -1852,7 +1854,7 @@ [(set (match_operand:DI 0 "register_operand" "=x") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "" + "TARGET_HARD_MUL" " { rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx); @@ -1869,7 +1871,7 @@ [(set (match_operand:DI 0 "register_operand" "=x") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "" + "TARGET_HARD_MUL" " { rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx); @@ -1889,7 +1891,8 @@ (match_operator:DI 4 "extend_operator" [(match_operand:SI 2 "register_operand" "d")]))) (clobber (match_scratch:SI 5 "=a"))] - "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])" + "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4]) + && TARGET_HARD_MUL" "* { if (GET_CODE (operands[3]) == SIGN_EXTEND) @@ -1908,7 +1911,8 @@ [(match_operand:SI 2 "register_operand" "d")]))) (clobber (match_scratch:DI 5 "=l")) (clobber (match_scratch:DI 6 "=h"))] - "TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])" + "TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4]) + && TARGET_HARD_MUL" "* { if (GET_CODE (operands[3]) == SIGN_EXTEND) @@ -1926,7 +1930,7 @@ (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32))))] - "" + "TARGET_HARD_MUL" " { rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx); @@ -1948,7 +1952,7 @@ (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))) (const_int 32))))] - "" + "TARGET_HARD_MUL" " { rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx); @@ -1975,7 +1979,7 @@ (const_int 32)]))) (clobber (match_scratch:SI 6 "=l")) (clobber (match_scratch:SI 7 "=a"))] - "GET_CODE (operands[3]) == GET_CODE (operands[4])" + "GET_CODE (operands[3]) == GET_CODE (operands[4]) && TARGET_HARD_MUL" "* { if (GET_CODE (operands[3]) == SIGN_EXTEND) @@ -1995,7 +1999,7 @@ (const_int 64)))) (clobber (match_scratch:DI 3 "=l")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT" + "TARGET_64BIT && TARGET_HARD_MUL" "dmult\\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI") @@ -2009,7 +2013,7 @@ (const_int 64)))) (clobber (match_scratch:DI 3 "=l")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT" + "TARGET_64BIT && TARGET_HARD_MUL" "dmultu\\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI") @@ -2238,7 +2242,7 @@ (clobber (match_scratch:SI 4 "=l")) (clobber (match_scratch:SI 5 "=h")) (clobber (match_scratch:SI 6 "=a"))] - "optimize" + "optimize && TARGET_HARD_DIV" " { emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2], @@ -2270,7 +2274,7 @@ (mod:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 6 "=a"))] - "optimize" + "optimize && TARGET_HARD_DIV" "div\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2286,7 +2290,7 @@ (clobber (match_scratch:DI 4 "=l")) (clobber (match_scratch:DI 5 "=h")) (clobber (match_scratch:DI 6 "=a"))] - "TARGET_64BIT && optimize" + "TARGET_64BIT && optimize && TARGET_HARD_DIV" " { emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2], @@ -2318,7 +2322,7 @@ (mod:DI (match_dup 1) (match_dup 2))) (clobber (match_scratch:DI 6 "=a"))] - "TARGET_64BIT && optimize" + "TARGET_64BIT && optimize && TARGET_HARD_DIV" "ddiv\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2334,7 +2338,7 @@ (clobber (match_scratch:SI 4 "=l")) (clobber (match_scratch:SI 5 "=h")) (clobber (match_scratch:SI 6 "=a"))] - "optimize" + "optimize && TARGET_HARD_DIV" " { emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2], @@ -2357,7 +2361,7 @@ (umod:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 6 "=a"))] - "optimize" + "optimize && TARGET_HARD_DIV" "divu\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2373,7 +2377,7 @@ (clobber (match_scratch:DI 4 "=l")) (clobber (match_scratch:DI 5 "=h")) (clobber (match_scratch:DI 6 "=a"))] - "TARGET_64BIT && optimize" + "TARGET_64BIT && optimize && TARGET_HARD_DIV" " { emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2], @@ -2396,7 +2400,7 @@ (umod:DI (match_dup 1) (match_dup 2))) (clobber (match_scratch:DI 6 "=a"))] - "TARGET_64BIT && optimize" + "TARGET_64BIT && optimize && TARGET_HARD_DIV" "ddivu\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2408,7 +2412,7 @@ [(trap_if (eq (match_operand 0 "register_operand" "d") (match_operand 1 "true_reg_or_0_operand" "dJ")) (match_operand 2 "immediate_operand" ""))] - "" + "TARGET_HARD_DIV" " { if (TARGET_MIPS16) @@ -2422,7 +2426,7 @@ [(trap_if (eq (match_operand 0 "register_operand" "d") (match_operand 1 "true_reg_or_0_operand" "dJ")) (match_operand 2 "immediate_operand" ""))] - "!TARGET_MIPS16" + "!TARGET_MIPS16 && TARGET_HARD_DIV" "* { rtx link; @@ -2467,7 +2471,7 @@ (match_operand 1 "true_reg_or_0_operand" "dJ")) (match_operand 2 "immediate_operand" "")) (clobber (reg:SI 24))] - "TARGET_MIPS16" + "TARGET_MIPS16 && TARGET_HARD_DIV" "* { rtx link; @@ -2501,7 +2505,7 @@ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" " { emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2])); @@ -2530,7 +2534,7 @@ (match_operand:SI 2 "nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" "div\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2542,7 +2546,7 @@ (match_operand:DI 2 "se_register_operand" "d"))) (clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" " { emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2])); @@ -2571,7 +2575,7 @@ (match_operand:DI 2 "se_nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" "ddiv\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "DI") @@ -2583,7 +2587,7 @@ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_scratch:SI 3 "=l")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" " { emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2])); @@ -2612,7 +2616,7 @@ (match_operand:SI 2 "nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=l")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" "div\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2624,7 +2628,7 @@ (match_operand:DI 2 "se_register_operand" "d"))) (clobber (match_scratch:DI 3 "=l")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" " { emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2])); @@ -2653,7 +2657,7 @@ (match_operand:DI 2 "se_nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=l")) (clobber (match_scratch:SI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" "ddiv\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "DI") @@ -2665,7 +2669,7 @@ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" " { emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2])); @@ -2685,7 +2689,7 @@ (match_operand:SI 2 "nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" "divu\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2697,7 +2701,7 @@ (match_operand:DI 2 "se_register_operand" "di"))) (clobber (match_scratch:DI 3 "=h")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" " { emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2])); @@ -2717,7 +2721,7 @@ (match_operand:DI 2 "se_nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:SI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" "ddivu\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "DI") @@ -2729,7 +2733,7 @@ (match_operand:SI 2 "register_operand" "d"))) (clobber (match_scratch:SI 3 "=l")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" " { emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2])); @@ -2749,7 +2753,7 @@ (match_operand:SI 2 "nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=l")) (clobber (match_scratch:SI 4 "=a"))] - "!optimize" + "!optimize && TARGET_HARD_DIV" "divu\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI") @@ -2761,7 +2765,7 @@ (match_operand:DI 2 "se_register_operand" "di"))) (clobber (match_scratch:DI 3 "=l")) (clobber (match_scratch:DI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" " { emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2])); @@ -2781,7 +2785,7 @@ (match_operand:DI 2 "se_nonmemory_operand" "di"))) (clobber (match_scratch:SI 3 "=l")) (clobber (match_scratch:SI 4 "=a"))] - "TARGET_64BIT && !optimize" + "TARGET_64BIT && !optimize && TARGET_HARD_DIV" "ddivu\\t$0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "DI") diff -u gcc-2.95.2/gcc/config/mips/t-elf.tigon gcc-2.95.2/gcc/config/mips/t-elf --- gcc-2.95.2/gcc/config/mips/t-elf.tigon Wed Apr 14 12:46:48 1999 +++ gcc-2.95.2/gcc/config/mips/t-elf Wed Apr 19 11:56:23 2000 @@ -7,36 +7,20 @@ # Suppress building libgcc1.a, since the MIPS compiler port is complete # and does not need anything from libgcc1.a. LIBGCC1 = +CROSS_LIBGCC1 = EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # Don't let CTOR_LIST end up in sdata section. CRTSTUFF_T_CFLAGS = -G 0 -# When building a cross compiler, put the mips16 support functions in -# libgcc1.a. -CROSS_LIBGCC1 = libgcc1-asm.a -LIB1ASMSRC = mips/mips16.S -LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \ - _m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \ - _m16fltsisf _m16fixsfsi \ - _m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \ - _m16extsfdf2 _m16trdfsf2 \ - _m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \ - _m16fltsidf _m16fixdfsi \ - _m16retsf _m16retdf \ - _m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \ - _m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \ - _m16stubsf9 _m16stubsf10 \ - _m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \ - _m16stubdf9 _m16stubdf10 - # We must build libgcc2.a with -G 0, in case the user wants to link # without the $gp register. -TARGET_LIBGCC2_CFLAGS = -G 0 +TARGET_LIBGCC2_CFLAGS = -G 0 -Dinhibit_libc # fp-bit and dp-bit are really part of libgcc1, but this will cause # them to be built correctly, so... [taken from t-sparclite] -LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c +# Also include the integer multiply & divide routines from muldiv.c +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c mulsi3.c divsi3.c modsi3.c udivsi3.c umodsi3.c dp-bit.c: $(srcdir)/config/fp-bit.c echo '#ifdef __MIPSEL__' > dp-bit.c @@ -53,11 +37,20 @@ echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c cat $(srcdir)/config/fp-bit.c >> fp-bit.c -# Build the libraries for both hard and soft floating point - -MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3 -MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3 -MULTILIB_MATCHES = msingle-float=m4650 +mulsi3.c divsi3.c modsi3.c udivsi3.c umodsi3.c: $(srcdir)/config/muldiv.c + echo "#define L_`basename $@ .c`" > $@ + echo '#define FINE_GRAINED_LIBRARIES' >> $@ + cat $(srcdir)/config/muldiv.c >> $@ + +# Build the libraries for little and big endian. +# Declare multilib paths for mips3 and hard-float/single-float +# (as the standard MIPS GCC does), but do not build those libraries. +# They cannot be built with the Alteon assembler. + +MULTILIB_OPTIONS = hard-float/single-float EL/EB mips1/mips3 +MULTILIB_DIRNAMES = hard-float single-float el eb mips1 mips3 +MULTILIB_MATCHES = +MULTILIB_EXCEPTIONS = *float*|*mips3* LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib diff -u gcc-2.95.2/gcc/config/muldiv.c.tigon gcc-2.95.2/gcc/config/muldiv.c --- gcc-2.95.2/gcc/config/muldiv.c.tigon Mon Apr 17 18:38:11 2000 +++ gcc-2.95.2/gcc/config/muldiv.c Wed Apr 19 11:58:30 2000 @@ -0,0 +1,183 @@ +/* This implements single integer multiplication and division for + targets without multiplication and division instructions. + + Copyright (C) 2000 Jamie Lokier + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with other files, + some of which are compiled with GCC, to produce an executable, + this library does not by itself cause the resulting executable + to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +/* Defining FINE_GRAINED_LIBRARIES allows one to select which routines + from this file are compiled via additional -D options. + + This avoids the need to pull in the entire fp emulation library + when only a small number of functions are needed. + + If FINE_GRAINED_LIBRARIES is not defined, then compile every + suitable routine. */ +#ifndef FINE_GRAINED_LIBRARIES +#define L_mulsi3 +#define L_divsi3 +#define L_modsi3 +#define L_udivsi3 +#define L_umodsi3 +#endif + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); + + +#ifdef L_mulsi3 +USItype +__mulsi3 (USItype u, USItype v) +{ + USItype result = 0; + while (u) + { + if (u & 1) + result += v; + v <<= 1; + u >>= 1; + } + return result; +} +#endif + +#if defined (L_divsi3) || defined (L_modsi3) \ + || defined (L_udivsi3) || defined (L_umodsi3) +static inline USItype +__udivmodsi4 (USItype a, USItype b, int want_remainder) +{ + USItype quotient, remainder; + + /* The end conditions are a little bit unrolled so we can use a + `quotient >= 0' sign bit test. Ideally we'd like to test the carry + bit after shifting but there's no way to write that in C. */ + quotient = 2; + remainder = ((SItype) a < 0); + a <<= 1; + do + { + if (remainder >= b) + { + remainder -= b; + quotient |= 1; + } + remainder = (remainder << 1) + ((SItype) a < 0); + a <<= 1; + quotient <<= 1; + } + while ((SItype) quotient >= 0); + + if (remainder >= b) + { + remainder -= b; + quotient |= 1; + } + remainder = (remainder << 1) + ((SItype) a < 0); + a <<= 1; + quotient <<= 1; + if (remainder >= b) + { + remainder -= b; + quotient |= 1; + } + + return want_remainder ? remainder : quotient; +} +#endif + +#ifdef L_divsi3 +SItype +__divsi3 (SItype a, SItype b) +{ + SItype result, flag = a ^ b; + a = __builtin_abs (a); + b = __builtin_abs (b); + result = __udivmodsi4 (a, b, 0); + if (flag < 0) + result = -result; + return result; +} +#endif + +#ifdef L_modsi3 +SItype +__modsi3 (SItype a, SItype b) +{ + SItype result, flag = a; + a = __builtin_abs (a); + b = __builtin_abs (b); + result = __udivmodsi4 (a, b, 1); + if (flag < 0) + result = -result; + return result; +} +#endif + +#ifdef L_udivsi3 +USItype +__udivsi3 (USItype a, USItype b) +{ + return __udivmodsi4 (a, b, 0); +} +#endif + +#ifdef L_udivsi3 +USItype +__umodsi3 (USItype a, USItype b) +{ + return __udivmodsi4 (a, b, 1); +} +#endif + +#if 0 /* Code to test the routines in this file. */ +#include +#include +int +main () +{ + int i; + for (i = 0; i < 1000000; i++) + { + USItype a = (random () >> 5) ^ (random () << 10); + USItype b = (random () >> 5) ^ (random () << 10); +#define CHECK(fmt, func, op) \ + if (func (a, b) != (op)) \ + printf ("Error: %s ("fmt", "fmt") = "fmt" (should be "fmt")\n", \ + #func, a, b, func (a, b), (op)); + CHECK ("%u", __mulsi3, a * b); + CHECK ("%u", __udivsi3, a / b); + CHECK ("%d", __umodsi3, a % b); + CHECK ("%d", __divsi3, ((SItype) a) / ((SItype) b)); + CHECK ("%d", __modsi3, ((SItype) a) % ((SItype) b)); + } + return 0; +} +#endif /* 0 */ diff -u gcc-2.95.2/gcc/longlong.h.tigon gcc-2.95.2/gcc/longlong.h --- gcc-2.95.2/gcc/longlong.h.tigon Wed Jan 6 21:44:39 1999 +++ gcc-2.95.2/gcc/longlong.h Thu Apr 20 01:47:22 2000 @@ -625,7 +625,7 @@ #endif /* __mc88110__ */ #endif /* __m88000__ */ -#if defined (__mips__) +#if defined (__mips__) && !defined (__mips_soft_mul) #define umul_ppmm(w1, w0, u, v) \ __asm__ ("multu %2,%3" \ : "=l" ((USItype) (w0)), \